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High-precision ADC testing is a challenging problem because of its stringent requirement on test signal's linearity. This work introduces a method using a nonlinear stimulus signal for testing linearity of high-resolution cyclic and pipelined ADCs by exploiting their architecture information. Simulation and experiments show that 16-bit ADCs can be tested to 1-LSB accuracy by using a 7-bit linear signal. This approach provides a solution to both the production and on-chip testing problems of high-resolution ADCs.
VLSI Test Symposium, 2007. 25th IEEE
Date of Conference: 6-10 May 2007