Scheduled System Maintenance:
On May 6th, system maintenance will take place from 8:00 AM - 12:00 PM ET (12:00 - 16:00 UTC). During this time, there may be intermittent impact on performance. We apologize for the inconvenience.
By Topic

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
6 Author(s)

In order to improve the testability of asynchronous NoCs, we have developed a design-for-test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused to establish high throughput TAMs. A special block, the generator-analyzer-controller (GAC) unit, has also been developed to generate test vectors, to control test flows, and to analyze the test results. This unit can be implemented on-chip or off-chip (in our experiments, it has been implemented off-chip). The operation of the test wrappers is controlled by a dedicated 2-bit configuration channel. Thanks to its scalability and versatility, the proposed architecture can be configured to adapt to any NoC topology and to any specific application.

Published in:

Networks-on-Chip, 2007. NOCS 2007. First International Symposium on

Date of Conference:

7-9 May 2007