Referenced Items are not available for this document.
A radical approach to high-speed on-chip communication between computational modules is proposed. Data communication is performed over multiple serial buses, where the time difference between events is used to encode and decode data on a number of wires. We present results obtained through a proof-of-concept implementation on FPGA and simulations on a 0.18mum technology
Published in:
Networks-on-Chip, 2007. NOCS 2007. First International Symposium on
Date of Conference: 7-9 May 2007
- Page(s):
- 65 - 74
- Print ISBN:
- 0-7695-2773-6
- INSPEC Accession Number:
- 9498385
- Conference Location :
- Princeton, NJ
- Digital Object Identifier :
- 10.1109/NOCS.2007.29
- Product Type:
- Conference Publications
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