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On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus

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2 Author(s)
Thomas William Ainsworth ; University of Southern California Los Angeles, USA ; Timothy Mark Pinkston

With the rise of multicore computing, the design of on-chip networks (or networks on chip) has become an increasingly important component of computer architecture. The cell broadband engine's element interconnect bus (EIB), with its four data rings and shared command bus for end-to-end control, supports twelve nodes - more than most mainstream on-chip networks, which makes it an interesting case study. As a first step toward understanding the design and performance of on-chip networks implemented within the context of a commercial multicore chip, this paper analytically evaluates the EIB network using conventional latency and throughput characterization methods as well as using a recently proposed 5-tuple latency characterization model for on-chip networks. These are used to identify the end-to-end control component of the EIB (i.e., the shared command bus) as being the main bottleneck to achieving minimal, single-cycle latency and maximal 307.2 GB/sec raw effective bandwidth provided natively by the EIB. This can be exacerbated by poorly designed cell software, which can have significant impact on the utilization of the EIB. The main findings from this study are that the end-to-end control of the EIB influenced by software running on the cell has inherent scaling problems and serves as the main limiter to overall network performance. Thus, end-to-end effects must not be overlooked when designing efficient networks on chip

Published in:

First International Symposium on Networks-on-Chip (NOCS'07)

Date of Conference:

7-9 May 2007