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A comparison of low power architectures for digital delay measurement

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4 Author(s)
Martin-Pirchio, F. ; Departamento de Ingenieria Electrica y Computadoras, Univ. Nacional del Sur, Bahia Blanca ; Chacon-Rodriguez, A. ; Julian, P. ; Mandolesi, P.

Two different versions of a method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz are compared in terms of their power dissipation. Power dissipation simulations are run on both versions from their layout on a 0.35mum technology. The second version shows a cut of 37% in total dissipation under the same test conditions.

Published in:

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Date of Conference:

9-11 March 2007

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