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Negative bias temperature instability (NBTI) has become a growing concern in nanometer technologies. It may reduce the lifetime of reliable operation of PMOS transistors in the design. Process variation has started impacting the nanometer ICs by reducing the parametric yield. Process variation together with NBTI can further reduce the reliable lifetime of ICs. Conventional ASIC design methodology uses pre-characterized standard cells to optimize the design as per specifications. The standard cells occupy nearly 75% of the chip real estate in a sea-of-gate design. Therefore process variation and NBTI tolerant robust standard cells may help in reducing the margin of performance variation thereby increasing the lifetime of reliable operation. The use of robust cells may further help in reducing the design time overhead. In this work, the authors model the combined effect of process variation and NBTI on intrinsic gate delay using a reduced dimension modeling technique. The authors use the models to optimize the standard cells in the presence of NBTI and process variations with a target lifetime of 10 years. Experimental results show that the use of optimized robust standard cells can considerably improve the tolerance of circuit in the self-timed sections of critical timing paths.