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Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan

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4 Author(s)
Zhipeng Liu ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing ; Jinian Bian ; Qiang Zhou ; Hui Dai

This article proposes an efficient algorithm by module duplication for integration of high-level synthesis and floorplan to optimize the interconnect delay and power. Module duplication can bring down the interconnect wire length among physical modules, thereby further reducing the interconnect delay and power. With the proper generosity of the area constraint, incremental high-level synthesis and floorplan procedures are proposed to perform iteratively for finding the best place for the duplicated module to be inserted. The key contribution of the algorithm lies in the fact that our designs are 20.8% more interconnect delay-efficient and 12.5% more interconnect power-efficient over the results produced by original design methods

Published in:

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Date of Conference:

9-11 March 2007

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