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Network processors are present in modern embedded systems that incorporate network capabilities, playing an important role in the design of routers. Architectures of network processors typically consist of heterogeneous hardware elements (processing units, memories and communication structures), software elements that implement protocols stacks, applications running on multiple uncertain scenarios along with unpredictable related traffic, consequently increasing the complexity of design space exploration task One form of helping the identification of efficient architectures during initial design stages is the use of analytical methods for system-level performance evaluation, as well as for individual components. In this work the authors present a method to enhance accuracy and fidelity of system-level performance analysis in obtaining the estimation of latency, buffer requirements and resource utilization, through improvements to a well-established modular performance analysis framework. A comparison of obtained results versus RTL simulation under realistic traffic is attained.