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Code-coverage Based Test Vector Generation for SystemC Designs

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2 Author(s)
Dias Junior, A. ; Dept. de Engenharia Eletronica, Univ. Fed. de Minas Gerais, Belo Horizonte ; Cecilio da Silva Junior, D.

This work presents a methodology for the automatic test vector generation for SystemC combinational designs based on code coverage analysis which is complementary to the functional testing. The method uses coverage information to generate test vectors capable of covering the portions of code not exercised by the black-box testing. Vectors are generated using an instrumented code followed by a numerical optimization method. This approach does not suffer from restrictions related to symbolic execution such as defining array reference values and loop boundaries, as the code is really executed together with the optimization. We expect this combined methodology to achieve total code coverage of the design and reduce the fault of omission problem, undetectable by structural testing alone.

Published in:

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Date of Conference:

9-11 March 2007