By Topic

Design and Analysis of Low Power Dynamic Bus Based on RLC simulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shanq-Jang Ruan ; National Taiwan University of Science and Technology ; Shang-Fang Tsai ; Yu-Ting Pai

In this paper, we propose a low power dynamic bus encoding scheme which simultaneously reduces the capacitive and inductive effects by the measurement of real RLC model. It should be noted that our method does not need a sufficient knowledge of the patterns on the bus. Our experimental results show that the proposed approach can save power consumption of the bus up to 12% compared to the nonencoded case. We also propose an area-aware scheme to optimize our circuits in terms of power consumption and area. The scheme can reduce the circuit area up to 29% while keeping almost the same power reduction

Published in:

IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)

Date of Conference:

9-11 March 2007