By Topic

Efficient VLSI Implementation of Memory-Based FFT Processors for DVB-T Applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chin-Long Wey ; Dept. of Electr. Eng., National Central Univ., Jhongli ; Wei-Chien Tang ; Shin-Yo Lin

This paper presents a radix-2 memory-based FFT processors, namely, MBFFTP, with a memory size of N words for large N complex points, where each word contains 24 bits. The developed MBFFTP meets DVB-T standard and can handle both 2K and 8K modes in the same architecture. The processors have been designed and implemented in TSMC 0.18mum 1P6M process. Results show that simple MBFFTP achieves a maximum work frequency of 173MHz, where its core chip area is approximately 1.80 mm with a core power consumption of 40.80 mW at 55 MHz for 2K mode and 48.16 mW at 65 MHz for 8K mode.

Published in:

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Date of Conference:

9-11 March 2007