By Topic

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hentschke, R. ; Instituto de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre ; Flach, G. ; Pinto, F. ; Reis, R.

This paper presents a cell placement algorithm for 3D-circuits. Compared to existing approaches, our placer has a number of new features that delivers more realism and improved wire length. First, the algorithm balances the tier utilization considering the effect of 3D-vias within two possible integration strategies: face-to-face and face-to-back. 3D-vias count is limited to an upper bound, that is sensible to the area of the 3D-via. Within the upper bound, the placer is free to add more 3D-vias, fact that delivers an improved wire length, as demonstrated experimentally in the paper. Our algorithm is based on a true 3D quadratic placement engine with a 3D cell shifting method to spread the cells out and on an iterative refinement step that improves wire length. Experimental results show that our algorithm can improve the wire length compared to a 2D solution provided by the FastPlace algorithm from 15% up to 27% in average.

Published in:

VLSI, 2007. ISVLSI '07. IEEE Computer Society Annual Symposium on

Date of Conference:

9-11 March 2007