Skip to Main Content
An innovative technique to model and simulate partial and dynamic reconfiguration is presented in this paper Developed from modifications of the SystemC kernel, this technique can either be used at transaction level (TLM) or at register transfer level (RTL). At TLM it allows the modeling and simulation of higher-level hardware and embedded software, while at RTL the dynamic system behavior can be observed at signals level. The provided set of instructions promises a reduction in the design cycle. Compared with traditional strategies, information about dynamic and adaptive behavior will be available in an earlier stage,. An established application from the automotive domain is analyzed and illustrates the potential of the technique at TLM. The acquired results will assist in the choice of the best cost/benefit tradeoff regarding FPGA chip area.