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Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM

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4 Author(s)
Di Guglielmo, G. ; Dipt. di Informatica, Univ. di Verona ; Fummi, F. ; Marconcini, C. ; Pravadelli, P.

A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state space by exploiting an easy-to-traverse extended finite state machine (FSM) model has been described. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the extended FSM. Testing of hard-to-detect faults is thus improved. The generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows also to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs

Published in:

Computers & Digital Techniques, IET  (Volume:1 ,  Issue: 3 )

Date of Publication:

May 2007

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