Gold Wire Bonding Induced Peeling in Cu/Low-k Interconnects: 3D Simulation and Correlations

Amongst solutions to connect the die to the package, thermosonic wire bonding process remains widely used. However, the introduction of low-k dielectric materials, and the feature size decrease of IC chips to follow Moore's law, pose great integration challenge. This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in both the gold wire and the copper/low-k stack have been evaluated and discussed. The modeling strategy also includes an in-house developed energy based analysis. For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, the effect of the bonding conditions has been studied. More precisely, it was found that the peeling failure rates are significantly dependant on the used wire types and their respective bonding parameters. In this paper, some numerical parameters are firstly discussed and the most suitable modeling strategy is proposed. Hence, typical results are presented, and the comparison of the peeling hazard induced by distinct bonding conditions is carried out. Simulations are then faced to experimental results and a good agreement is found. In addition to that, the complementary nature of the energy based failure criteria is highlighted through a clearer determination of the forecasted location of the failed interface in the IC stack. Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.