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One key failure root cause during wafer production is the electrical test by probing all interconnects of each die of the wafer. The probing process can result in excessive damage of the back end of line (BEOL) wafer layers underneath the probe pad, especially if brittle low-k dielectrics are used. The industry is trying to reduce design limitations for these under pad areas. A 3D sub-modeling simulation approach has been used to investigate stress states in layers below the probe pad. The dynamic behavior of the needle is determined by modal analysis. Its representation and calculation is done by an analytical model using the modal superposition method. These small, specialized simulation models help to distribute the simulation effort, by handling specific aspects of the real process, such as the contact problem, needle dynamics and homogenization of fine structures. The results showed that the needle dynamics can be neglected during further studies. The static load due to the maximum displacement of the needle tip during the probe event is one magnitude higher then any dynamic driven load.