By Topic

Simulation and Design of JFET-Controlled Carbon Nanotube Field Emitter Arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Qiong Shui ; Southern California Univ., Los Angeles, CA ; Chan, C.-Y. ; Gundersen, M.A. ; Umstattd, R.J.
more authors

Summary form only given. The introduction of Spindt microtip cold cathodes has led to interest in the pursuit of electron beam sources for flat panel displays and vacuum microelectronics devices. Mo, Si, SiC, GaN, and carbon nanotubes (CNTs), have been proposed as cathode materials to achieve high current density and low-voltage operation. Among those materials, carbon nanotubes are important candidates because they are stable at high temperatures, can have high electrical and thermal conductivity, a high aspect ratio and they exhibit ballistic electron transport. A corresponding key issue is how to improve emission stability and controllability. Active devices, such as MOSFETs and JFETs, integrated with Si or metal microtips, were experimentally proven effective in the improvement of emission current stability when the active device operates in the saturation region. In this paper, a novel structure design - JFET-controlled CNTs - is proposed and is being fabricated. JFETs will be used to control the stability of the emission current, which is extremely sensitive to the local surface's electrical field and work function, as well as to prevent disruptively excessive emission current. Two main issues for the design are: (1) JFET fabrication must be compatible with the last high-temperature step of CNT growth by plasma enhanced chemical vapor deposition (PECVD) at 700degC; (2) JFETs should have a high breakdown voltage. The standard 2-D semiconductor device simulator ATLAS was used to simulate and analyze the avalanche breakdown of JFETs at different ion implantation energies (150 keV and 200 keV, respectively) and of different JFET structures. Our simulation results show that a 200 keV ion implantation energy and a tall post JFET structure will give optimal voltage performance. We will also present detailed process steps and important considerations for the planned fabrication and testing of these devices

Published in:

Plasma Science, 2005. ICOPS '05. IEEE Conference Record - Abstracts. IEEE International Conference on

Date of Conference:

20-23 June 2005