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Design of several asynchronous-logic macrocells for a low-voltage micropower cell library

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3 Author(s)
K. -s. Chong ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore ; B. -h. Gwee ; J. S. Chang

Several asynchronous-logic macrocells for a cell library for low-voltage (1.1 V) power-critical applications are described. The intended application is for the realisation of the datapath of an embedded asynchronous digital signal processor in low-voltage power-critical digital hearing instruments where the speed is relatively low, <5 MHz. The macrocells are two 2-bit and three 16-bit adders, a 16times16-bit truncated parallel multiplier and a 16-bit accumulator. Compared to reported 2-bit adders, one of the 2-bit adders features the lowest energy-delay product (EDP), whereas the other features the lowest energy (power/MHz). Among the three proposed 16-bit adders, two of them feature the lowest EDP compared to the reported designs, and their completion detection circuit is very simple (an OR gate). The truncated parallel 16times16-bit multiplier features the lowest energy multiplier in the literature and this is achieved by truncation and by means of a proposed integrated latch-cum-adder (latch adder) that virtually eliminates the spurious switching in the adder block. The accumulator features the lowest energy accumulator, also by means of the latch adder embodied therein. All macrocells are verified by computer simulations and on the basis of measurements on prototype ICs

Published in:

IET Circuits, Devices & Systems  (Volume:1 ,  Issue: 2 )