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ESD Protection Design by Using Only 1×VDD Low-Voltage Devices for Mixed-Voltage I/O Buffers with 3×VDD Input Tolerance

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2 Author(s)
Ming-Dou Ker ; Institute of Electronics, National Chiao-Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan. E-mail: ; Chang-Tzu Wang

A new electrostatic discharge (ESD) protection design by using only 1timesVDD low-voltage devices for mixed-voltage I/O buffer with 3timesVDD input tolerance is proposed. A special ESD detection circuit has been proposed to improve ESD protection efficiency of ESD clamp device by substrate-triggered technique to achieve high ESD level. This design has been successfully verified in a 0.13-mum CMOS process to provide an excellent circuit solution for on-chip ESD protection in the mixed-voltage I/O buffers with 3timesVDD input tolerance.

Published in:

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Date of Conference:

13-15 Nov. 2006