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43μW 6GHz CMOS Divide-by-3 Frequency Divider Based on Three-Phase Harmonic Injection Locking

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2 Author(s)
Motoyoshi, M. ; Univ. of Tokyo, Kashiwa ; Fujishima, M.

A harmonic injection-locked divider (HILD) is effective for realizing a low-power phase-locked loop (PLL) circuit because the high-frequency output of a voltage-controlled oscillator (VCO) is down-converted into a low-frequency signal instantaneously. Conventional resonator-based HILDs, however, occupy a large chip area and exhibit a narrow locking range because either an LC or short-stub resonator is required. Ring-oscillator-based HILDs, on the other hand, operate at a relatively low frequency, again with a narrow locking range. In this study, a new HILD based on three-phase harmonic injection locking is proposed, which realizes a small chip area, a low power consumption, and a wide locking range. As a result of fabrication with 0.18 μm CMOS, a divide-by-three HILD is realized with a power consumption of 43 μW, a maximum operating frequency of 6 GHz, and a locking range of 80% at a supply voltage of 0.7 V. The core size is 10.8 μm x 10.5 μm.

Published in:

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Date of Conference:

13-15 Nov. 2006