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A 6.5-mW 5-Gbps On-Chip Differential Transmission Line Interconnect with a Low-Latency Asymmetric Tx in a 180nm CMOS Technology

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5 Author(s)
Ishii, T. ; Integrated Res. Inst., Tokyo Inst. of Technol., Yokohama ; Ito, H. ; Kimura, M. ; Okada, K.
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This paper proposes an on-chip differential- transmission-line (DTL) interconnect to reduce delay and power consumption in long global interconnects. The DTL interconnect can transmit signals at near light-of-speed with small power dissipation of Tx. The proposed DTL interconnect consists of Tx, DTL and Rx, and an asymmetric Tx is employed to reduce offset delay in Tx. In the measurement result, 5 Gbps signal transmission can be achieved through 3 mm-length interconnect, and delay and total power consumption are 140 ps and 6.5 mW, respectively. A 180 nm standard CMOS process was utilized. Figure of merit (FoM) for on-chip interconnects is proposed to evaluate delay and power consumption. The proposed DTL interconnect is compared with the conventional RC, DTL and optical interconnects, and it achieves the highest FoM at more than 5 mm length.

Published in:

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Date of Conference:

13-15 Nov. 2006