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A Versatile Multimedia Functional Unit Design Using the Spurious Power Suppression Technique

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4 Author(s)
Kuan-Hung Chen ; Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi ; Yu-Min Chen ; Yuan-Sun Chu ; Jiun-In Guo

This paper presents a versatile multimedia functional unit (VMFU) which can compute six arithmetic operations, i.e. addition, subtraction, multiplication, MAC, interpolation, and SAD with different configurations. The VMFU is constructed on the basis of a row-based modified Booth encoding multiplier which consumes the lowest power among others according to our transistor-level simulations. Besides, we apply the spurious power suppression technique (SPST) to the proposed VMFU to decrease the wasted dynamic power dissipation. From the transistor-level simulations, the proposed VMFU dissipates 0.0142 mW/MHz under a 0.18 mum/1.8V CMOS technology. Adopting the SPST can reduce 24% power consumption with only a 15% area overhead.

Published in:

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Date of Conference:

13-15 Nov. 2006

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