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A pulsed Ultra Wideband receiver front end for the 3.1 to 10.6 GHz band is implemented in a main-stream 0.18 mum CMOS technology. The monolithic UWB receiver incorporates a mixed-signal multiphase clock generator together with an analog demodulation and amplifier chain on a die of 1.4times1.4 mm. A dual in-phase/quadrature (I/Q) receiver approach, enabling phase modulation of the UWB impulses, is presented and experimentally demonstrated. The design is optimized to cope with the large bandwidths at the RF input stage and the output buffers are able to directly drive an external analog-to-digital converter (ADC). The receiver consumes 120 mW from a single 1.8 V power supply and is capable to detect 107 M pulses per second. Data transfer up to 428 Mbit/s is possible when a 16-PSK modulation scheme is applied, but can be easily scaled down according to the actual signal-to-noise (SNR) parameters.