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The U1traSPARC T1: A Power-Efficient High-Throughput 32-Thread SPARC Processor

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2 Author(s)
Leon, A.S. ; Sun Microsyst. Inc., Sunnyvale ; Sheahan, D.

Throughput computing represents a new paradigm in processor design focusing on maximizing overall throughput of commercial workloads while addressing increasing demands for improved power and cooling in today's data centers. The first generation of "Niagara" SPARC processors implements a power-efficient chip multithreading (CMT) architecture, which combines eight 4-threaded 64 b cores, a high bandwidth interconnect crossbar, a shared 3 MB L2 Cache and four double-width DDR2 DRAM interfaces. Implemented in 90 nm CMOS technology, the 378 mm2 die consumes only 63 W at 1.2 GHz. The UltraSPARC Tl based systems are oriented to a wide variety of applications, including WebServers, data and application servers, Java applications, search, streaming video and Telco applications.

Published in:

Solid-State Circuits Conference, 2006. ASSCC 2006. IEEE Asian

Date of Conference:

13-15 Nov. 2006

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