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The design of system on chip (SoC) is getting more and more complex. One of the challenges is to find out an interconnection topology and a set of architecture parameters which minimize the area and power consumption while satisfying design constraint. The object of this paper is to propose a new design space exploration methodology for network on chip which use (1) hardware emulation for fast performance evaluation (2) actual post synthesis place and route for area results and (3) actual optimal implementation frequency to compute execution time rather than number of cycles. Based on these values, a statistical tool based on principal component analysis brings productivity gains for network on chip designer to quickly select network on chip components appropriate parameters value. Generally speaking the paper introduces fully automatic network on chip implementation cross-layer analysis in an integrated manner. Case studies validate our approach.