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Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

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4 Author(s)
Fawnizu Azmadi Hussin ; Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai Science ; Yoneda, T. ; Orailoglu, A. ; Fujiwara, H.

An integrated test scheduling methodology for multiprocessor system-on-chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology.

Published in:

Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific

Date of Conference:

23-26 Jan. 2007