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A 0.35um CMOS 1,632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI

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2 Author(s)
Watanabe, M. ; Dept. of Syst. Innovation & Informatics, Kyushu Inst. of Technol., Fukuoka ; Kobayashi, F.

A zero-overhead dynamic optically reconfigurable gate array VLSI (ZO-DORGA-VLSI) has been developed. It is based on a concept using junction capacitance of photodiodes and load capacitance of gates constructing a gate array as configuration memory and removing static memory function to store a context. In this paper, the performance of a 1,632 ZO-DORGA-VLSI, which was fabricated using a 0.35 mum - 4.9 mm square CMOS process chip, is presented. In addition, the design of an over 10,000 ZO-DORGA-VLSI is presented.

Published in:

Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific

Date of Conference:

23-26 Jan. 2007

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