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A Multi-Drop Transmission-Line Interconnect in Si LSI

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5 Author(s)
Junki Seita ; Integrated Research Institute, Tokyo Institute of Technology, 4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan. Phone: +81-45-924-5031, FAX: +81-45-924-5166, e-mail: ; Hiroyuki Ito ; Kenichi Okada ; Takashi Sato
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This paper proposes a branching method for on-chip transmission line (TL) interconnects, which can reduce delay and power of global interconnects. A 6-mm-long TL interconnect with a branch is fabricated by using a 0.18 mum standard Si CMOS process, and the measurement result performs 4Gbps signal transmission.

Published in:

2007 Asia and South Pacific Design Automation Conference

Date of Conference:

23-26 Jan. 2007