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Fast and Accurate OPC for Standard-Cell Layouts

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3 Author(s)
Pawlowski, D.M. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana-Champaign, IL ; Liang Deng ; Wong, M.D.F.

Model based optical proximity correction (OPC) has become necessary at 90nm technology node and beyond. Cell-wise OPC is an attractive technique to reduce the mask data size as well as the prohibitive runtime of full-chip OPC. As feature dimensions have gotten smaller, the radius of influence for edge features has extended further into neighboring cells such that it is no longer sufficient to perform cellwise OPC independent of neighboring cells, especially for the critical layers. The methodology described in this work accounts for features in neighboring cells and allows a cellwise approach to be applied to cells with a printed gate length of 45nm with the projection that it can also be applied to future technology nodes. OPC-ready cells are generated at library creation (independent of placement) using a boundary-based technique. Each cell has a tractable number of OPC-ready versions due to an intelligent characterization of standard cell layout features. Total number of cells with boundaries in the OPC-ready library only increases linearly with the number of cells in the original library. Results are very promising: the average edge placement error (EPE) for all metal1 features in 100 layouts is 0.731nm which is less than 1 % of metal1 width, creating similar levels of lithographic accuracy while obviating any of the drawbacks inherent in layout specific full-chip model-based OPC. For even small circuits, there were runtime reductions of up to 100times and a potential 35times decrease in mask data size.

Published in:

Design Automation Conference, 2007. ASP-DAC '07. Asia and South Pacific

Date of Conference:

23-26 Jan. 2007

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