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3D Power Delivery for Microprocessors and High-Performance ASICs

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5 Author(s)
Jian Sun ; Department of Electrical, Computer, Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180-3590, USA. Telephone: (518)276-8297; Fax: (518)276-6226; E-mail: ; Jian-Qiang Lu ; Giuliano, D. ; Chow, T.P.
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Conventional power delivery methods for microprocessors and high-performance ASICs have fundamental limitations in meeting the power requirements of future IC technologies due to large interconnect parasitics. A new three-dimensional (3D) power delivery approach along with a cellular power supply architecture is proposed as a possible solution to the problems of conventional 2D power delivery. Different 3D integration technologies or possible power-processor integration applications are reviewed, and important 3D design partitioning considerations are discussed. A fully monolithic, two-phase interleaved buck converter design having the potential to be used as a basic building block in a cellular architecture to meet steady-state and dynamic regulation requirements of future processors is presented. Each cell of the converter is designed for 500 mA rated output current, operates at 200 MHz switching frequency, and achieves a control bandwidth of about 10 MHz. Design trade-offs, implementation methods, and prototype results including chip area, loss breakdown, efficiency, as well as dynamic responses to load step changes are presented. Scaling-up of the design through parallel operation of a large number of such standard converter cells is discussed, and the benefits of interleaved operation in drastically reducing the input and output filter size are quantified.

Published in:

Applied Power Electronics Conference, APEC 2007 - Twenty Second Annual IEEE

Date of Conference:

Feb. 25 2007-March 1 2007