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Modern microprocessors can rapidly shift between a sleep state and full load operation, placing a heavy requirement on the voltage regulator to stabilize its output voltage. High repetitive rate transient poses new challenges for voltage regulator design. The old "rule of thumb" approaches for capacitor selection may not be optimized in terms of physical size, performance, and cost. In this paper, output impedance oriented voltage regulator design methodology and procedure is presented to pursue the cost effective solution.