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A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme

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3 Author(s)
Chua-Chin Wang ; Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung ; Ching-Li Lee ; Wun-Ji Lin

The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-kb 4-T SRAM is measured to consume 0.32 mW in the standby mode, and a 3.8-ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:54 ,  Issue: 5 )

Date of Publication:

May 2007

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