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Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder

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2 Author(s)
Fei Sun ; Dept. of Electr., Comput. & Syst. Eng., Rensselaer Polytech. Inst., Troy, NY ; Tong Zhang

Although it possesses reduced computational complexity and great power saving potential, conventional adaptive Viterbi algorithm implementations contain a global best survivor path metric search operation that prevents it from being directly implemented in a high-throughput state-parallel decoder. This limitation also incurs power and silicon area overhead. This paper presents a modified adaptive Viterbi algorithm, referred to as the relaxed adaptive Viterbi algorithm, that completely eliminates the global best survivor path metric search operation. A state-parallel decoder VLSI architecture has been developed to implement the relaxed adaptive Viterbi algorithm. Using convolutional code decoding as a test vehicle, we demonstrate that state-parallel relaxed adaptive Viterbi decoders, versus Viterbi counterparts, can achieve significant power savings and modest silicon area reduction, while maintaining almost the same decoding performance and very high throughput

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:54 ,  Issue: 5 )