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High-performance 0.5 mu m n-MOS technology with thin nitrided oxide as gate dielectric

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7 Author(s)
da Costa, J.C. ; Dept. Microelectron., CENG, Grenoble, France ; Guegan, G. ; Lerme, M. ; Rey, A.
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0.5 mu m n-MOS devices and circuits have been fabricated successfully using a thin plasma-nitrided silicon dioxide 13 nm thick, with a nitrogen content at the surface. Individual devices show very good and reproducible behaviour. 101-stage ring oscillators with 46 ps gate delay per stage have been obtained, showing that these new dielectrics will be perfectly compatible with future submicronic technologies.

Published in:

Electronics Letters  (Volume:25 ,  Issue: 17 )

Date of Publication:

17 Aug. 1989

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