By Topic

Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jit-Hung Sung, R. ; Adv. Micro Devices Inc., Sunnyvale, CA ; Elliott, D.G.

We present a design methodology for synchronous single-rail domino logic circuits, where inverting and nonmonotonic logic functions can be integrated into a pipeline with almost zero overhead relative to classic domino counterparts. This logic family, called clock-logic (CL) domino, is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL domino algorithmic logic unit (ALU) at 1 GHz under high skew conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 5 )