Referenced Items are not available for this document.
A method of communicating a unified pareto, we call "Grand Pareto," for technology-wide failure mechanisms that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical failure analysis and statistical yield analysis techniques to create a single message for the process community to drive the yield improvement efforts. The methodology has been successfully deployed at IBM where it has been assisting identification of key yield detractors for several high-end microprocessors in volume production
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:20
,
Issue:
2
)
Date of Publication: May 2007
- Page(s):
- 87 - 100
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 9449517
- Digital Object Identifier :
- 10.1109/TSM.2007.896641
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 07 May 2007
- Issue Date :
- May 2007
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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