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We present the development of a 64 channel readout ASIC called DEDIX for high count rate position-sensitive measurements using semiconductor detectors. The ASIC is designed in 0.35 mum CMOS process and its total area is 3400 times 5000 mum2. The DEDIX has a binary readout architecture. Each channel is built of a charge sensitive amplifier (CSA) with a pole-zero cancellation circuit, a shaper, two independent discriminators and two independent 20-bit counters. The size of the input device in CSA has been optimized for a detector capacitance in the range of 1-3 pF per strip. An equivalent noise charge of 110 el rms has been achieved for a total detector capacitance of 1 pF at the shaper peaking time of 160 ns. Internal correction DAC implemented in each channel independently ensures the low spread of effective threshold of discriminators at 0.4 mV on one sigma level. The mean gain in the multichannel ASIC is 54 muV/el, with a good uniformity from channel to channel (sd/mean = 0.8%). Low noise performance and high rate capability have been demonstrated by the measurement up to and above 1 MHz of average rate of input signals.