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Configurable Hardware-Effcient Interface Circuit for Multi-Sensor Microsystems

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4 Author(s)
Chao Yang ; Michigan State Univ., East Lansing ; Mason, A. ; Jinwen Xi ; Peixin Zhong

A new, high resolution, multi-sensor interface circuit is presented to read out up to eight resistive or capacitive sensors while sharing configurable circuits to achieve hardware and power efficiency. A non-balanced (NB) bridge approach was adopted for both resistive and capacitive interfaces, eliminating the need for finely tunable on-chip components to balance the bridge. The shared pre-amp and programmable gain signal-conditioning stages are formed with switched capacitor circuits. Through a carefully designed clock scheme, a sample-and-hold (S/H) function is realized without a dedicated S/H circuit. The effects of op-amp offset and parasitic capacitance at the inputs are suppressed, and undesirable disturbance of the bridge DC point is avoided during resistance measurement. The 0.53 x 0.75mm circuit was implemented in 0.18mum CMOS and requires only 300muA from a 1.8V supply. It has the size and power efficiency to implement a front-end sensor interface system-on-chip with an embedded controller.

Published in:

Sensors, 2006. 5th IEEE Conference on

Date of Conference:

22-25 Oct. 2006