By Topic

Statistical analysis of Power Delay Estimation in adder circuit using non-clocked pass gate families

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Senthilpari, C. ; Fac. of Eng. & Technol., Multimedia Univ., Melaka ; Singh, A.K. ; Arokiasamy, A.

In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation. The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique. The different logic cells, used for various pass gates circuit design styles are evaluated in terms of area, propagation delay, power dissipation and propagation delay product. The design styles are compared by performing detailed transistor-level simulations on a benchmark circuit (CSA adder) using DSCH3 and Microwind3. We have analysed the results in a statistical way. We have compared our results with the various published results of adder circuits. We found that the speed of the proposed circuit is enhanced and power consumption as well as the area has reduced tremendously due to multiplexing control input technique. Comparing the simulated results with other pass logic designs, it was observed that in all existing logic CPL is a promising candidate for future logic design.

Published in:

Electrical and Computer Engineering, 2006. ICECE '06. International Conference on

Date of Conference:

19-21 Dec. 2006