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Root Locus Plots and Iterative Decoding

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1 Author(s)
Kellett, C.M. ; Hamilton Inst., Nat. Univ. of Ireland, Maynooth

A well known class of error correction codes called low-density parity-check (LDPC) codes have been the subject of a great deal of recent study in the coding community as a result of their ability to approach Shannon's fundamental capacity limit. Crucial to the performance of these codes is the use of an iterative decoder. We describe LDPC codes and the decoding algorithm and make a connection between the fixed points of the decoding algorithm and the well-known root locus plot. Via two example LDPC codes, we describe the insights afforded by the root locus plot

Published in:

Decision and Control, 2006 45th IEEE Conference on

Date of Conference:

13-15 Dec. 2006