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Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction

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2 Author(s)
Tai-Chen Chen ; Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei ; Yao-Wen Chang

To handle modern routing with nanometer effects, we need to consider designs with variable wire/via widths and spacings, for which gridless-routing approaches are desirable due to its great flexibility. In this paper, we introduce a gridless-routing model that can obtain design-rule-correct paths and avoid redundant wires. Besides, we propose an enhanced model for the gridless-routing model to reduce the solution space and the runtime. Based on the enhanced gridless-routing model, we present the first multilevel full-chip gridless detailed router (called MGR). The router integrates global routing, detailed routing, and congestion estimation together at each level of multilevel routing. It can handle designs with nonuniform wire/via widths and spacings and consider routability and optical-proximity correction. Experimental results show that MGR achieves the best routing solutions in smaller running times than previous works, based on a set of commonly used benchmarks (with uniform and nonuniform wire widths) and a set of real industrial benchmarks (with a versatile set of design rules)

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:26 ,  Issue: 6 )