By Topic

Algorithms for high-level synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Paulin, P.G. ; Bell-Northern Res., Ottawa, Ont., Canada ; Knight, J.P.

Synthesis algorithms that offer a technique for scheduling operations and allocating registers and buses in light of both timing constraints and available hardware resources are presented. They enhance current scheduling techniques by using a global priority function that minimizes storage, interconnections, and functional unit cost. Algorithms for allocating registers and buses minimize storage and interconnection costs and take into account the interdependence of both tasks. The algorithms are also applicable to more than one method of synthesis; although first implemented in the HAL system, they have since been integrated into more specialized high-level synthesis systems.<>

Published in:

Design & Test of Computers, IEEE  (Volume:6 ,  Issue: 6 )