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An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection

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2 Author(s)
Xiaoding Chen ; Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ. ; Hsiao, M.S.

We present a novel scan architecture for simultaneously reducing test application time and test power (both average and peak power). Unlike previous works where the scan chain is partitioned only based on the excitation properties of the flip-flops (FFs), our work considers both the excitation and propagation properties of the scan FFs. In the proposed scan architecture, the scan chain is partitioned to maximize the overlapping between the excitation and propagation on different fault sets. The scan architecture also allows the entire set of detectable faults in the circuit under test (CUT) to be detected with only a portion of the scan elements active at a time, and thereby completely eliminates the need for the "serial full-scan" mode which is inefficient for both the test time and test power. Experimental results show that by introducing minimal hardware overhead, and without sacrificing fault coverage, an average peak power reduction of 22.8%, average power reduction of 41.6%, and an average reduction of 18.5% on the test application time can be achieved, compared with the ordinary full-scan architecture

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:15 ,  Issue: 4 )

Date of Publication:

April 2007

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