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A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes

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2 Author(s)
Zhongfeng Wang ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR ; Zhiqiang Cui

This paper presents a memory efficient partially parallel decoder architecture suited for high rate quasi-cyclic low-density parity-check (QC-LDPC) codes using (modified) min-sum algorithm for decoding. In general, over 30% of memory can be saved over conventional partially parallel decoder architectures. Efficient techniques have been developed to reduce the computation delay of the node processing units and to minimize hardware overhead for parallel processing. The proposed decoder architecture can linearly increase the decoding throughput with a small percentage of extra hardware. Consequently, it facilitates the applications of LDPC codes in area/power sensitive high-speed communication systems

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:15 ,  Issue: 4 )