Referenced Items are not available for this document.
This paper presents a novel context-based adaptive variable length coding (CAVLC) architecture based on split and shared VLC look up table technique. The architecture is prototyped in Verilog HDL, simulated and synthesized for Xilinx Virtex II FPGA. The experimental result shows that the proposed architecture is capable of processing CIF frame sequences in real-time and is smaller than any of the real-time architectures proposed so far. The maximum speed of the core is around 60 MHz
Published in:
Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on
Date of Conference: Oct. 2006
- Page(s):
- 368 - 371
- ISSN :
- 1520-6130
- E-ISBN :
- 1-4244-0383-9
- Print ISBN:
- 1-4244-0383-9
- INSPEC Accession Number:
- 9398986
- Conference Location :
- Banff, Alta.
- Digital Object Identifier :
- 10.1109/SIPS.2006.352610
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