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Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories

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3 Author(s)
Wei Liu ; Sch. of Electr. Eng., Seoul Nat. Univ. ; Junrye Rho ; Wonyong Sung

As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories, there is growing call for fast and compact error correction code (ECC) circuit with minimum impact on memory access time and chip area. This paper presents a high-throughput and low-power ECC scheme for MLC NAND flash memories. The BCH encoder and decoder architecture features byte-wise processing and a low complexity key equation solver using a simplified Berlekamp-Massey algorithm. Resource sharing and power reduction techniques are also applied. Synthesized using 0.25-mum CMOS technology in a supply voltage of 2.5 V, the proposed BCH (4148,4096) encoder/decoder achieves byte-wise processing, and it needs an estimated cell area of 0.2 mm2, and an average power of 3.18 mW with 50 MB/s throughput

Published in:

Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on

Date of Conference:

Oct. 2006