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Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor

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4 Author(s)
Beucher, N. ; Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que. ; Belanger, N. ; Savaria, Y. ; Bois, G.

This paper describes an application-specific instruction set for a configurable processor to accelerate motion compensated frame rate conversion (MC-FRC) algorithms based on block motion estimation (BME). The proposed instruction set is generic enough to support many MC-FRC algorithms. The performance gain obtained from this instruction set is described and explained. The new instructions are used to implement two BME algorithms: the full search (FS) algorithm and the one-dimensional full search (ODFS) algorithm. The obtained acceleration factor is about one hundred in the case of the FS algorithm and about forty in the case of ODFS. This paper describes the new instruction set and explains these results by describing more precisely how the acceleration is performed. This paper also shows that the acceleration reached can lead to real-time performance on video streams that have a bandwidth similar to NTSC using processors currently available

Published in:

Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on

Date of Conference:

2-4 Oct. 2006

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