By Topic

H.264 Video Decoder Design: Beyond RTL Design Implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Youngsoo Kim ; Electr. & Comput. Eng. Dept., North Carolina State Univ., Raleigh, NC ; Edmonson, William

We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is designed based on configurable processor. The configurable processor was used to complement the existing functional units with instruction extensions for the H.264 hardware kernel. Secondly, we profile the H.264 application to capture the amount of data traffic among modules. We will use this information to guide the placement of H.264 hardware modules in the dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in a dataflow architecture. With both our design methodologies, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time with maximum design flexibility

Published in:

Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on

Date of Conference:

Oct. 2006