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Digit-Serial Systolic Architectures for Inversions over GF(2m)

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1 Author(s)
Zhiyuan Yan ; Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA

Digit-serial architectures for finite field arithmetic operations are of interest since hardware costs can be optimized by minimizing the digit size to satisfy throughput requirements. Based on a reformulation of the extended Euclidean algorithm, we design digit-serial systolic architectures with digit size L for inversions over GF(2m) using a systematic approach. Compared with previously proposed digit-serial inversion architectures, our new architectures require significantly less hardware and reduce critical path delays by 50% while achieving the same throughput L/m and latency. Unlike previously proposed digit-serial inversion architectures, for which L has to be a divisor of m, our systematic approach is applicable even when L is not a divisor of m

Published in:

Signal Processing Systems Design and Implementation, 2006. SIPS '06. IEEE Workshop on

Date of Conference:

Oct. 2006