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The Field Programmable Processor Array (FPPA) is a reconfigurable processor chip developed for NASA for high-throughput, low-power on-board processing of streaming data. The FPPA implements a synchronous dataflow computational model, with 16 on-board processing elements. Each processing element can perform multiplication simultaneously with addition/subtraction or logic operations, as well as data path formatting and data path switching. An integral microsequencer executes an internally-stored program. The chips are designed to be tiled, effectively extending the dataflow pipeline across multiple chips to accommodate larger data processing problems than a single chip can manage. The architecture has been validated through simulation on several computational challenge problems. In many cases, the processor is able to sustain one output sample per clock cycle. A suite of support software includes a simulator, assemblers, and design entry tools. A prototype has been fabricated in a 0.25mu radiation-hard by design (RHBD) process.